1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating an integrated circuit transistor with a diffused source/drain region vertically separated from another source/drain region.
2. Description of the Related Art
Insulated gate field effect transistors ("IGFET"), such as metal oxide semiconductor field effect transistors ("MOSFET"), are some of the most commonly used electronic components in modern integrated circuits. Embedded controllers, microprocessors, analog-to-digital converters, and many other types of devices now routinely include millions of MOSFETs. The dramatic proliferation of MOSFETs in integrated circuit design can be traced to their high switching speeds, potentially low power dissipation, and adaptability to semiconductor process scaling.
A typical MOSFET implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical MOSFET, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then lithographically patterned and anisotropically etched back to the upper surface of the substrate leaving a gate electrode stack consisting of a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the gate electrode stack, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode stack acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode stack.
In conventional processing, the gate oxide layer and electrode are formed on the semiconductor wafer in a generally parallel orientation relative to the horizontal plane of the wafer. The source and drain are formed on opposite sides of the gate electrode stack with the lateral spacing between the source and the drain defining a channel region for the MOSFET. In conjunction with several other factors, the width of the channel region or "channel length" determines the ultimate speed of the MOSFET. As a general rule of thumb, smaller channel widths translate into both higher switching speeds and smaller die areas.
The minimum channel length attainable in conventional processing is dictated, in large part, by the width of the gate oxide layer and the gate electrode. As with other horizontal dimensions on a given wafer, the minimum achievable width of the gate oxide layer and gate electrode is determined by the resolution of the photolithographic system used to pattern the wafer. The resolution of an optical photolithographic system is normally an aggregate of a number of physical mechanisms, such as lens aberrations, light spectrum, and diffraction effects. However, diffraction effects constitute the dominant limitation to resolution, particularly in sub 1.0 .mu.m processing.
The fabrication of increasingly smaller features such as gate electrode stacks relies on the availability of increasingly higher resolution optical lithography equipment. Designers of optical lithography equipment have employed several techniques to combat the deleterious effects of light diffraction. Some of these techniques include decreasing the wave length of the illuminating light, increasing the numerical aperture of the system, increasing the contrast of the resist by modifying resist chemistry or by creating entirely new resists, and adjusting the coherence of the optical system. Even with the availability of these various techniques for increasing the resolution of optical lithography equipment, the best of conventional optical lithography systems have a resolution limit of about 0.2 .mu.m.
Electron beam lithography has occasionally been used as a substitute for optical lithography in circumstances where the resolution limits of the prevailing optical lithography techniques prevented successful fabrication of a particular integrated circuit. However, there are several drawbacks associated with electron beam lithography, including resolution limitations associated with electrons forward scattered in the resist and back scattered from the substrate, swelling, which often occurs during development of a negative e-beam resist, extremely slow processing times when compared to optical projection systems, and significantly higher cost of electron beam lithography systems compared to optical steppers.
X-ray lithography has also been used occasionally in place of optical lithography to obtain resolutions in the sub 1 .mu.m area. However, as with electron beam lithography, certain technical difficulties have prevented X-ray lithography from supplanting optical lithography as the lithographic process of choice in mass produced integrated circuits. X-ray reticles have proven to be extremely difficult to reliably manufacture.
The present invention is directed to overcoming or reducing one or more of the foregoing disadvantages.